1. Field of the Invention
The present invention relates to a row decoder circuit having a CMOS structure and more particularly, to a row decoder circuit used in a dynamic memory.
2. Description of the Prior Art
FIG. 1 is a diagram showing an example of a structure of a conventional row decoder circuit, which is disclosed in, for example, IEEE, Journal of Solid-State Circuits, vol. SC-21, No. 3, June 1986, p. 384.
In FIG. 1, a conventional row decoder circuit comprises a first stage for decoding applied address signals, an inverter stage for inverting and amplifying an output of the first stage and transmitting the same, and a driver stage responsive to an output of the inverter stage for transmitting a word line driving signal to a word line.
The first stage comprises a p channel MOS transistor 1 having a gate receiving a reset signal .phi..sub.p for providing reset timing of the row decoder circuit, and n channel MOS transistors 3 to 4 each having a gate receiving one of address signals A.sub.0 to A.sub.n selected from external address signals, and connected in series with the p channel MOS transistor 1 and connected in series with each other. The p channel MOS transistor 1 has one conduction terminal connected to a power supply potential V.sub.cc and the n channel MOS transistor 4 has other conduction terminal connected to a ground potential.
The inverter stage comprises a p channel MOS transistor 5 and an n channel MOS transistor 6, which are complimentarily connected, each having a gate electrode connected to a node (referred to as a node N1 hereinafter) of the p channel MOS transistor 1 and the n channel MOS transistor 3. The p channel MOS transistor 5 has one conduction terminal connected to the power supply potential V.sub.cc and the n channel MOS transistor 6 has other conduction terminal connected to the ground potential.
The driver stage comprises n channel MOS transistors 8 to 9 each having a gate receiving the power supply potential V.sub.cc for transmitting the output (the potential at a node N2) of the inverter stage, and n channel MOS transistors 10 to 11 each having a gate receiving each of signals transmitted by the n channel MOS transistors 8 to 9 for transmitting respective word line driving signals .phi..sub.xo to .phi..sub.xi to word lines WL1 to WL2 connected thereto. The word line driving signals .phi..sub.xo to .phi..sub.xi are formed in accordance with the external address signals. Thus, a single word line is selected by a combination of the address signals A.sub.0 to A.sub.n and the word line driving signals .phi..sub.xo to .phi..sub.xi. In addition, a plurality of word lines are connected to an output of the row decoder circuit. As a pitch between word lines is made finer in an increased integrity of a memory, it becomes difficult to achieve a structure in which a single row decoder circuit is provided with a single word line. Thus, a plurality of word lines are used in common by a single unit row decoder circuit to accommodate the reduced pitch between word lines.
FIG. 2 is a waveform diagram of timing showing operation of the row decoder circuit shown in FIG. 1. Referring now to FIGS. 1 and 2, description is made on the conventional row decoder circuit.
When the reset signal .phi..sub.p rises and the p channel MOS transistor 1 is turned off, the row decoder circuit is rendered active. The row decoder circuit is selected in accordance with a combination of address signals subsequently applied. More specifically, if and when all the address signals A.sub.0 to A.sub.n connected to the row decoder circuit are at a "1" level, the MOS transistors 3 to 4 included in the row decoder circuit are turned on so that the node N1 is discharged. As a result, the row decoder circuit is selected. On the other hand, if at least one of the address signals A.sub.0 to A.sub.n applied thereto is at a "0" level, at least one of the MOS transistors 3 to 4 is turned off, so that the node N1 is not discharged and held at a high potential level. The potential appearing on the node N1 is transmitted to the node N2 through the inverter stage comprising the transistors 5 and 6. The potential on the node N2 is transmitted to gate electrodes of the MOS transistors 10 to 11 for driving word lines through the transistors 8 to 9, respectively. More specifically, if the row decoder circuit is selected, a high potential is applied to the gate electrodes of the MOS transistors 10 to 11. If the row decoder circuit is not selected, a low potential is applied to the gate electrodes of the MOS transistors 10 to 11. Thus, only if the row decoder circuit is selected, the transistors 10 to 11 are turned on, so that the word line driving signals .phi..sub.xo to .phi..sub.xi formed in accordance with the external address signals are transmitted to the word lines WL1 to WL2, respectively. Thus, the potential on a word line receiving the word line driving signal at an "H" level rises, so that a single word line is selected. The transistors 8 and 9 perform functions of decreasing stray capacitance of a gate electrode of each transistor by rendering non-conductive between the node N2 and the gate electrodes of the transistors 10 to 11 when the word line driving signals .phi..sub.xo to .phi..sub.xi are applied in the selected state, in order to improve the signal transmission characteristics of the transistors 10 to 11 due to the self-bootstrap effect.
Since the conventional row decoder circuit has the above described structure, there were some problems. For example, while the reset signal .phi..sub.p is at a high level (the row decoder circuit is rendered active), the state of the address signals must be held. When the address signals are received in a time-divisional manner for a row and a column as in a dynamic memory, two sets of address buffers are required for row address signals and column address signals. In addition, address signal lines for transmitting the row address signals and the column address signals to the row decoder circuit and a column decoder circuit within a memory, respectively, must be separately provided and interconnected, so that the area of a semiconductor chip having a semiconductor memory device or devices formed is increased due to the area of the interconnection, the area for constituting the buffer and the like.